Central processing unit (CPU) simulation is often very slow. The virtualization technology is used for accelerating the CPU simulation, for example, SoftSDV and Simics of Intel can run based on a compatible CPU platform. Most instructions of new generation CPUs can directly run in old generation CPUs by using the virtualization technology, which is faster than solely software simulation technologies (e.g., binary translation of Qemu and interpretative translation of Bochs). Generally in the CPU field, most instructions of the new generation CPUs are consistent with those of the old generation CPUs, that is, backward compatibility is kept. However, the situation of the GPU field is different.
The operation on a GPU mainly includes two kinds:
1) accessing GPU registers, wherein the GPU generally includes a large amount of registers for controlling various running modes and states of the GPU, including display, rendering, power management and the like, and the GPU registers are generally mapped to a memory address space of a system in a memory mapped input/output (MMIO) mode; and
2) submitting GPU instructions, wherein the executions are generally stored in multiple circular buffers or batch buffers classified manner and then concurrently executed by rendering engines inside the GPU, and executing the instructions is a main working mode of the GPU.
The GPU simulation is more complex and slower than the CPU simulation:
Firstly, in the hardware design of the GPU seldom, support for virtualization is seldom considered. In contrast, nearly all existing CPUs have a characteristic of relatively perfect hardware-assisted virtualization. Thus, the GPU simulation is more difficult from the perspective of hardware characteristic support.
Secondly, the instruction design of the GPU does not guarantee sufficient backward compatibility as CPUs. When the GPU is upgraded, the semantics of instructions may be redefined. Thus, it becomes very difficult to directly run new generation GPU instructions in old generation GPUs, and vice versa.